Display panel and display apparatus including the same

ABSTRACT

A display panel may include: a substrate including a front display area, a corner display area extending from a corner of the front display area, and a peripheral area outside the corner display area, where the corner display area includes a first corner display area and a second corner display area; a first corner driving circuit positioned in the second corner display area and electrically connected to each of a front pixel arranged in the front display area and a corner pixel arranged in the first corner display area; a second corner driving circuit positioned in the second corner display area, electrically connected to the corner pixel arranged in the first corner display area, and not electrically connected to the front pixel; and a load portion positioned in the peripheral area and electrically connected to the second corner driving circuit.

This application claims priority to Korean Patent Application No.10-2021-0036756, filed on Mar. 22, 2021, and all the benefits accruingtherefrom under 35 U.S.C. § 119, the content of which in its entirety isherein incorporated by reference.

BACKGROUND 1. Field

One or more embodiments relate to a display apparatus, and moreparticularly, to a display panel, in which a display area is expanded todisplay an image on not only a front area but also on side areas and/orcorner areas, and a display apparatus including the display panel.

2. Description of the Related Art

Display apparatuses may visually display data. Display apparatuses maybe used as displays for small products such as mobile phones or may beused as displays for large products such as televisions.

Recently, as the use of display apparatuses has diversified, variousattempts have been made to improve the quality and functions of displayapparatuses. For example, research and development on curved displayapparatuses, foldable display apparatuses, and rollable displayapparatuses are being actively conducted. Also, display areas areexpanding, and non-display areas are being reduced in size. Accordingly,various methods have been derived to design the form of displayapparatuses.

SUMMARY

One or more embodiments provide a display panel, in which a display areais expanded to display an image even on side areas and/or corner areas,and a display apparatus including the display panel.

According to an embodiment, a display panel includes a substrateincluding a front display area, a corner display area extending from acorner of the front display area a, and a peripheral area outside thecorner display area, where the corner display area includes a firstcorner display area and a second corner display area, the first cornerdisplay area includes extension portions extending in a direction awayfrom the front display area, and cutout portions are defined in thefirst corner display area between the extension portions, a first cornerdriving circuit positioned in the second corner display area andelectrically connected to each of a front pixel arranged in the frontdisplay area and a corner pixel arranged in the first corner displayarea, a second corner driving circuit positioned in the second cornerdisplay area, electrically connected to the corner pixel arranged in thefirst corner display area, and not electrically connected to the frontpixel, and a load portion positioned in the peripheral area andelectrically connected to the second corner driving circuit.

According to an embodiment, the extension portions may include a firstextension portion in which the load portion is not positioned and asecond extension portion in which the load portion is positioned, thecorner pixel electrically connected to the first corner driving circuitmay be arranged in the first extension portion along an extendingdirection of the first extension portion, and the corner pixelelectrically connected to the second corner driving circuit may bearranged in the second extension portion along an extending direction ofthe second extension portion.

According to an embodiment, the display panel may further include avoltage line positioned in the second corner display area, a cornervoltage line extending in the extending direction of the secondextension portion in the second extension portion, and including an endelectrically connected to the voltage line and another end electricallyconnected to the load portion, and a corner signal line extending in theextending direction of the second extension portion in the secondextension portion, and including an end electrically connected to thesecond corner driving circuit and another end electrically connected tothe load portion.

According to an embodiment, the load portion may include a firstconductive layer and a second conductive layer, where the secondconductive layer may be disposed on the first conductive layer andoverlapping the first conductive layer, the another end of the cornersignal line may be electrically connected to the first conductive layer,and the another end of the corner voltage line may be electricallyconnected to the second conductive layer.

According to an embodiment, the corner pixel may be electricallyconnected to a corner pixel circuit including at least one thin-filmtransistor and at least one storage capacitor, the at least onethin-film transistor may include a semiconductor layer, a gate electrodeoverlapping the semiconductor layer, and a source electrode and a drainelectrode which are electrically connected to the semiconductor layer,the at least one storage capacitor may include a lower electrode and anupper electrode, where the lower electrode may be disposed in a samelayer as the gate electrode, and the upper electrode may overlap thelower electrode, the first conductive layer and at least one selectedfrom the gate electrode and the lower electrode may have a same layerstructure as each other and include a same material as each other, andthe second conductive layer and the upper electrode may have a samelayer structure and include a same material as each other.

According to an embodiment, the load portion may include a firstconductive layer, a second conductive layer disposed on the firstconductive layer and overlapping the first conductive layer, and a thirdconductive layer disposed on the second conductive layer and overlappingthe second conductive layer, the another end of the corner signal linemay be electrically connected to the first conductive layer, and theanother end of the corner voltage line may be electrically connected tothe third conductive layer.

According to an embodiment, the corner pixel may be electricallyconnected to a corner pixel circuit including at least one thin-filmtransistor and at least one storage capacitor, the at least onethin-film transistor may include a semiconductor layer, a gate electrodeoverlapping the semiconductor layer, and a source electrode and a drainelectrode which are electrically connected to the semiconductor layer,the at least one storage capacitor may include a lower electrode and anupper electrode, where the lower electrode may be disposed in a samelayer as the gate electrode, and the upper electrode overlapping thelower electrode, the first conductive layer and the semiconductor layermay have a same layer structure as each other and include a samematerial as each other, the second conductive layer and at least oneselected from the gate electrode and the lower electrode may have a samelayer structure as each other and include a same material as each other,and the third conductive layer and the upper electrode may have a samelayer structure as each other and include a same material as each other.

According to an embodiment, when viewed in a direction perpendicular toan upper surface of the substrate, a shape of an outer edge of the loadportion may correspond to a shape of an outer edge of an extensionportion in which the load portion is positioned, among the extensionportions.

According to an embodiment, one load portion may be arranged in eachsecond extension portion.

According to an embodiment, two load portions may be arranged in eachsecond extension portion.

According to an embodiment, the corner pixel arranged in the secondcorner display area may overlap the first corner driving circuit or thesecond corner driving circuit.

According to an embodiment, the display area may further include a sidedisplay area extending from a side surface of the front display area,and a side pixel may be arranged in the side display area.

According to an embodiment, a display apparatus includes a display panelincluding a front display area, a corner display area extending from acorner of the front display area and bent at a preset radius ofcurvature, and a peripheral area outside the corner display area, wherethe corner display area includes a first corner display area and asecond corner display area, and a cover window covering the displaypanel and having a shape corresponding to a shape of the display panel,wherein the display panel includes a first corner driving circuitpositioned in the second corner display area and electrically connectedto each of a front pixel arranged in the front display area and a cornerpixel arranged in the first corner display area, a second corner drivingcircuit positioned in the second corner display area, electricallyconnected to the corner pixel arranged in the first corner display area,and not electrically connected to the front pixel, and a load portionpositioned in the peripheral area and electrically connected to thesecond corner driving circuit.

According to an embodiment, the first corner display area may includeextension portions extending in a direction away from the front displayarea, the extension portions may include a first extension portion inwhich the load portion is not positioned and a second extension portionin which the load portion is positioned, the corner pixel electricallyconnected to the first corner driving circuit may be arranged in thefirst extension portion along an extending direction of the firstextension portion, and the corner pixel electrically connected to thesecond corner driving circuit may be arranged in the second extensionportion along an extending direction of the second extension portion.

According to an embodiment, the display apparatus may further include avoltage line positioned in the second corner display area, a cornervoltage line extending along an extending direction of the secondextension portion in the second extension portion, and including an endelectrically connected to the voltage line and another end electricallyconnected to the load portion, and a corner signal line extending alongan extending direction of the second extension portion in the secondextension portion, and including an end electrically connected to thesecond corner driving circuit and another end electrically connected tothe load portion.

According to an embodiment, the load portion may include a firstconductive layer and a second conductive layer, the second conductivelayer may be disposed on the first conductive layer and overlapping thefirst conductive layer, the another end of the corner signal line may beelectrically connected to the first conductive layer, and the anotherend of the corner voltage line may be electrically connected to thesecond conductive layer.

According to an embodiment, the corner pixel may be electricallyconnected to a corner pixel circuit including at least one thin-filmtransistor and at least one storage capacitor, the at least onethin-film transistor may include a semiconductor layer, a gate electrodeoverlapping the semiconductor layer, and a source electrode and a drainelectrode which are electrically connected to the semiconductor layer,the at least one storage capacitor may include a lower electrode and anupper electrode, where the lower electrode may be disposed in a samelayer as the gate electrode, and the upper electrode may overlap thelower electrode, the first conductive layer and at least one selectedfrom the gate electrode and the lower electrode may have a same layerstructure and include a same material as each other, and the secondconductive layer and the upper electrode may have a same layer structureand include a same material as each other.

According to an embodiment, the load portion may include a firstconductive layer, a second conductive layer disposed on the firstconductive layer and overlapping the first conductive layer, and a thirdconductive layer disposed on the second conductive layer and overlappingthe second conductive layer, the another end of the corner signal linemay be electrically connected to the first conductive layer, and theanother end of the corner voltage line may be electrically connected tothe third conductive layer.

According to an embodiment, the corner pixel may be electricallyconnected to a corner pixel circuit including at least one thin-filmtransistor and at least one storage capacitor, the at least onethin-film transistor may include a semiconductor layer, a gate electrodeoverlapping the semiconductor layer, and a source electrode and a drainelectrode which are electrically connected to the semiconductor layer,the at least one storage capacitor may include a lower electrode and anupper electrode, where the lower electrode may be disposed in a samelayer as the gate electrode, and the upper electrode may overlap thelower electrode, the first conductive layer and the semiconductor layermay have a same layer structure as each other and include a samematerial as each other, the second conductive layer and at least oneselected from the gate electrode and the lower electrode may have a samelayer structure as each other and include a same material as each other,and the third conductive layer and the upper electrode may have a samelayer structure as each other and include a same material as each other.

According to an embodiment, on a plan view, a shape of an outer edge ofthe load portion may correspond to a shape of an outer edge of anextension portion in which the load portion is positioned, among theextension portions.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of certain embodiments of the disclosurewill be more apparent from the following description taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a schematic perspective view of a part of a display apparatus,according to an embodiment;

FIGS. 2A to 2C are schematic cross-sectional views of a part of thedisplay apparatus of FIG. 1;

FIG. 3A is a schematic plan view of a part of a display panel that maybe included in the display apparatus of FIG. 1;

FIG. 3B is an enlarged view of the encircled portion of FIG. 3A;

FIG. 4 is a schematic cross-sectional view of a part of a display panel,according to an embodiment;

FIG. 5 is a schematic cross-sectional view of a part of a display panel,according to an embodiment;

FIG. 6A is an equivalent circuit diagram of a subpixel according to anembodiment;

FIG. 6B is an equivalent circuit diagram of a subpixel according to analternative embodiment;

FIG. 7 is an enlarged schematic plan view of a part of a display panel,according to an embodiment;

FIG. 8 is an enlarged schematic plan view of a part of a display panel,according to an embodiment;

FIG. 9 is a schematic plan view of some of extension portions, accordingto an embodiment;

FIG. 10 is a schematic plan view of some of extension portions,according to an alternative embodiment;

FIG. 11 is a schematic cross-sectional view of a part of an extensionportion, according to an embodiment;

FIG. 12 is a schematic cross-sectional view of a part of an extensionportion, according to an alternative embodiment; and

FIG. 13 is a schematic cross-sectional view of a part of a load portion,according to an embodiment.

DETAILED DESCRIPTION

The invention now will be described more fully hereinafter withreference to the accompanying drawings, in which various embodiments areshown. This invention may, however, be embodied in many different forms,and should not be construed as limited to the embodiments set forthherein. Rather, these embodiments are provided so that this disclosurewill be thorough and complete, and will fully convey the scope of theinvention to those skilled in the art. Like reference numerals refer tolike elements throughout.

As the disclosure allows for various changes and numerous embodiments,certain embodiments will be illustrated in the drawings and described inthe detailed description. Effects and features of the disclosure, andmethods for achieving them will be clarified with reference toembodiments described below in detail with reference to the drawings.However, the disclosure is not limited to the following embodiments andmay be embodied in various forms.

It will be understood that, although the terms “first,” “second,”“third” etc. may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer or section from another element, component, region, layer orsection. Thus, “a first element,” “component,” “region,” “layer” or“section” discussed below could be termed a second element, component,region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting. As used herein,“a”, “an,” “the,” and “at least one” do not denote a limitation ofquantity, and are intended to include both the singular and plural,unless the context clearly indicates otherwise. For example, “anelement” has the same meaning as “at least one element,” unless thecontext clearly indicates otherwise. “At least one” is not to beconstrued as limiting “a” or “an.” “Or” means “and/or.” As used herein,the term “and/or” includes any and all combinations of one or more ofthe associated listed items. Also, an expression such as “at least oneof A and B” indicates A, B, or A and B. It will be further understoodthat the terms “comprises” and/or “comprising,” or “includes” and/or“including” when used in this specification, specify the presence ofstated features, regions, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, regions, integers, steps, operations, elements,components, and/or groups thereof.

It will be understood that when an element is referred to as being “on”another element, it can be directly on the other element or interveningelements may be therebetween. In contrast, when an element is referredto as being “directly on” another element, there are no interveningelements present.

Sizes of elements in the drawings may be exaggerated or contracted forconvenience of explanation. In addition, because sizes and thicknessesof elements in the drawings are arbitrarily illustrated for convenienceof explanation, the disclosure is not limited thereto.

When a certain embodiment may be implemented differently, a particularprocess order may be performed differently from the described order. Forexample, two consecutively described processes may be performedsubstantially at the same time or may be performed in an order oppositeto the described order.

It will be understood that when a layer, region, or element is referredto as being “connected to” another layer, region, or element, it may be“directly connected to” the other layer, region, or element or may be“indirectly connected to” the other layer, region, or element with oneor more intervening layers, regions, or elements therebetween. Forexample, it will be understood that when a layer, region, or element isreferred to as being “electrically connected to” another layer, region,or element, it may be “directly electrically connected to” the otherlayer, region, or element and/or may be “indirectly electricallyconnected to” the other layer, region, or element with one or moreintervening layers, regions, or elements therebetween.

The x-axis, the y-axis, and the z-axis are not limited to three axes ofthe rectangular coordinate system and may be interpreted in a broadersense. For example, the x-axis, the y-axis, and the z-axis may beperpendicular to one another or may represent different directions thatare not perpendicular to one another.

The embodiments will now be described more fully with reference to theaccompanying drawings. When describing embodiments with reference to theaccompanying drawings, the same or corresponding elements are denoted bythe same reference numerals and a redundant description thereof will beomitted.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thedisclosure, and will not be interpreted in an idealized or overly formalsense unless expressly so defined herein.

Embodiments are described herein with reference to cross sectionillustrations that are schematic illustrations of idealized embodiments.As such, variations from the shapes of the illustrations as a result,for example, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments described herein should not be construed aslimited to the particular shapes of regions as illustrated herein butare to include deviations in shapes that result, for example, frommanufacturing. For example, a region illustrated or described as flatmay, typically, have rough and/or nonlinear features. Moreover, sharpangles that are illustrated may be rounded. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the precise shape of a region and are notintended to limit the scope of the claims.

Hereinafter, embodiments of the invention will be described in detailwith reference to the accompanying drawings.

FIG. 1 is a schematic perspective view of a part of a display apparatus1, according to an embodiment, and FIGS. 2A to 2C are schematiccross-sectional views of a part of the display apparatus 1 of FIG. 1.

In detail, FIGS. 2A and 2B respectively correspond to cross-sectionalviews of the display apparatus 1 taken along an x-direction and ay-direction of FIG. 1, and FIG. 2C illustrates a cross-section in whichcorner display areas CDA are respectively arranged on opposing sides ofa front display area FDA in the display apparatus 1.

An embodiment of the display apparatus 1, which displays a moving imageor a still image, may be various apparatuses with a display screen, suchas not only portable electronic apparatuses, such as mobile phones,smartphones, tablet personal computers (“PC”s), smartwatches, watchphones, mobile communication terminals, electronic notebooks, electronicbooks, portable multimedia players (“PMP”s), navigation systems, andultra-mobile PCs (“UMPC”s), but also televisions, laptop computers,monitors, advertisement boards, and Internet of things (“IOT”)apparatuses.

In an embodiment, as illustrated in FIG. 1, the display apparatus 1 mayinclude a display area DA and a peripheral area PA outside the displayarea DA.

The display area DA may include a front display area FDA, a side displayarea SDA, and a corner display area CDA. A plurality of pixels PXincluding light-emitting elements may be arranged in each of the frontdisplay area FDA, the side display area SDA, and the corner display areaCDA, and an image may be displayed through the pixels PX. Thus, in suchan embodiment, the display apparatus 1 may display an image on front,side, and/or corner portions.

The front display area FDA is an area of the display area DA positionedon a front portion of a display panel 10. Front pixels PXf may bearranged in the front display area FDA. The front display area FDA mayhave a non-bendable and flat shape. FIG. 1 illustrates an embodimentwhere the front display area FDA has a rectangular shape including ashort side in a first direction (e.g., the x-direction) and a long sidein a second direction (e.g., the y-direction), but one or moreembodiments are not limited thereto. In one embodiment, for example, thefront display area FDA may be formed in an arbitrary shape, such as arectangular shape, a polygonal shape other than the rectangular shape, acircular shape, an oval shape, or the like, in which corners where ashort side and a long side meet are rounded.

The side display area SDA is an area of the display area DA positionedon a side portion of the display panel 10. Side pixels PXs may bearranged in the side display areas SDA. The side display area SDA may bean area extending from one side of the front display area FDA. In anembodiment, the side display area SDA may include a first side displayarea SDA1, a second side display area SDA2, a third side display areaSDA3, and/or a fourth side display area SDA4 extending from respectivesides (first to fourth sides) of the front display area FDA.

The side display area SDA may have a certain radius of curvature and mayhave a bent shape. In an embodiment, as shown in FIGS. 2A and 2B, boththe first side display area SDA1 and the fourth side display area SDA4have a first radius of curvature R1, and both the second side displayarea SDA2 and the third side display area SDA3 have a second radius ofcurvature R2, but one or more embodiments are not limited thereto. In analternative embodiment, the first to fourth side display areas SDA1,SDA2, SDA3, and SDA4 may have a same radius of curvature as each other.In another alternative embodiment, at least two of the first to fourthside display areas SDA1, SDA2, SDA3, and SDA4 may have different radiiof curvature from each other.

The corner display area CDA is an area of the display area DA positionedon a corner portion of the display panel 10. Corner pixels PXc may bearranged in the corner display areas CDA. The corner display area CDAmay be between the side display areas SDA adjacent to each other. In oneembodiment, for example, as illustrated in FIG. 1, the corner displayarea CDA may be between the first side display area SDA1 and the secondside display area SDA2, between the second side display area SDA2 andthe fourth side display area SDA4, between the third side display areaSDA3 and the fourth side display area SDA4, and/or between the thirdside display area SDA3 and the first side display area SDA1.

Referring to FIG. 2C, the corner display area CDA may have a thirdradius of curvature R3 and may have a bent shape. In an embodiment, thethird radius of curvature R3 may vary according to position. In such anembodiment, a change in the third radius of curvature R3 may depend onradii of curvature of the side display areas SDA adjacent to each other.In one embodiment, for example, the third radius of curvature R3 of thecorner display area CDA between the first side display area SDA1 and thesecond side display area SDA2 may depend on the first radius ofcurvature R1 of the first side display area SDA1 and the second radiusof curvature R2 of the second side display area SDA2. In one embodiment,for example, where the first radius of curvature R1 is less than thesecond radius of curvature R2, the third radius of curvature R3 of thecorner display area CDA may gradually increase in a direction from thefirst side display area SDA1 to the second side display area SDA2. Insuch an embodiment, the third radius of curvature R3 of the cornerdisplay area CDA may vary in a range of the first radius of curvature R1or more to the second radius of curvature R2 or less.

In an embodiment, the resolution of the corner display area CDA and/orthe resolution of the side display area SDA may be relatively lowcompared to the resolution of the front display area FDA. In such anembodiment, the number of corner pixels PXc arranged per unit area inthe corner display area CDA and/or the number of side pixels PXsarranged per unit area in the side display area SDA may be less than thenumber of front pixels PXf arranged per unit area in the front displayarea FDA. In an alternative embodiment, the resolution of the cornerdisplay area CDA and/or the resolution of the side display area SDA maybe the same as or relatively higher than the resolution of the frontdisplay area FDA.

The peripheral area PA may be a non-display area that does not displayan image. The peripheral area PA may surround at least part of thedisplay area DA. In one embodiment, for example, the peripheral area PAmay entirely surround the display area DA. In an embodiment, variouswirings for transmitting electrical signals to be applied to the displayarea DA may be located in the peripheral area PA. In such an embodiment,part of a circuit portion for controlling electrical signals to beapplied to the display area DA may be located in the peripheral area PA.

Referring to FIGS. 2A to 2C, an embodiment of the display apparatus 1may include the display panel 10 and a cover window 20 arranged ordisposed on the display panel 10.

The cover window 20 may cover and protect the display panel 10. Thecover window 20 may include a transparent material. The cover window 20may include, for example, glass or plastic. In an embodiment where thecover window 20 includes plastic, the cover window 20 may have aflexible property.

A shape of the cover window 20 may correspond to a shape of the displayapparatus 1. In one embodiment, for example, where the display apparatus1 includes the side display area SDA and the corner display area CDA,the cover window 20 may include a side area corresponding to the sidedisplay area SDA and a corner area corresponding to the corner displayarea CDA. The side area and the corner area of the cover window 20 maybe bent with a certain curvature. In such an embodiment, the curvatureof the side area and/or the curvature of the corner area of the coverwindow 20 may be a constant curvature or a variable curvature.

The display panel 10 may be arranged or disposed under the cover window20. In an embodiment, the cover window 20 and the display panel 10 maybe coupled to each other through an adhesive member (not illustrated).The adhesive member may be an optically clear adhesive film (“OCA”) oran optically clear resin (“OCR”).

FIG. 3A is a schematic plan view of a part of the display panel 10 thatmay be included in the display apparatus of FIG. 1, and FIG. 3B is anenlarged view of the encircled portion of FIG. 3A.

For reference, FIG. 3A illustrates an embodiment in a state before theside display area SDA and the corner display area CDA of the displaypanel 10 are bent, and as illustrated in FIG. 1, the side display areaSDA and the corner display area CDA may be bent.

In an embodiment, as illustrated in FIG. 3A, the display panel 10 mayinclude a substrate 100 and components on the substrate 100.

The substrate 100 may include the display area DA including the frontdisplay area FDA, the side display area SDA, and the corner display areaCDA, and the peripheral area PA outside the display area DA. A pluralityof pixels may be arranged or disposed on the display area DA, and eachof the pixels may be configured as or defined by a set of a plurality ofsubpixels. In an embodiment, each of the pixels may include subpixels,each including a light-emitting element that emits red, green, blue,and/or white light.

A plurality of front pixels PXf are arranged on the front display areaFDA. A front image may be displayed on the front display area FDA by thefront pixels PXf. In one embodiment, for example, the front pixels PXfmay be positioned at a point crossing a gate line GL extending in thefirst direction (e.g., the x-direction) and a data line DL extending inthe second direction (e.g., the y-direction), but not being limitedthereto. In such an embodiment, the gate line GL is configured totransmit an electrical control signal to a pixel circuit included in thepixels. The gate line GL may include a scan line configured to transmita scan signal and/or an emission control line configured to transmit anemission control signal.

The side display area SDA may be arranged at upper, lower, left, andright sides of the front display area FDA. The side display area SDA mayextend from each side of the front display area FDA. A plurality of sidepixels PXs are arranged in the side display area SDA. A side image maybe displayed on the side display area SDA by the side pixels PXs. Theside image may form an entire image together with the front image, orthe side image may be an image independent from the front image.

The corner display area CDA may be arranged in an area extending fromcorners of the front display area FDA. The corner display area CDA maybe between two side display areas SDA. A plurality of corner pixels PXcare arranged in the corner display area CDA. A corner image may bedisplayed on the corner display area CDA by the corner pixels PXc. Thecorner image may form an entire image together with the front imageand/or the side image, or the corner image may be an image independentfrom the front image and/or the side image.

In an embodiment, as shown in FIG. 3B, the corner display area CDA mayinclude a first corner display area CDA1 and a second corner displayarea CDA2. The first corner display area CDA1 may be arranged closer toan edge of the substrate 100 than the second corner display area CDA2,and the second corner display area CDA2 may be between the first cornerdisplay area CDA1 and the front display area FDA.

In an embodiment, a corner driving circuit CDRV may be arranged in thesecond corner display area CDA2 in addition to the corner pixels PXc. Inan embodiment, the corner pixels PXc arranged in the second cornerdisplay area CDA2 may overlap the corner driving circuit CDRV.

The corner driving circuit CDRV may provide a control signal (e.g., ascan signal and/or an emission control signal) for driving the cornerpixels PXc arranged in the corner display area CDA. In an embodiment, atleast part of the corner driving circuit CDRV may provide a controlsignal for driving the front pixels PXf arranged in the front displayarea FDA and/or the side pixels PXs arranged in the side display areaSDA. The corner driving circuit CDRV includes a first corner drivingcircuit CDRV1 and a second corner driving circuit CDRV2.

The first corner driving circuit CDRV1 is a corner driving circuit CDRVthat is simultaneously electrically connected to a pixel circuitconfigured to drive the corner pixels PXc and a pixel circuit configuredto drive the front pixels PXf. The gate line GL connected to the firstcorner driving circuit CDRV1 may extend in a direction from both sidesof the first corner driving circuit CDRV1 to the front display area FDAand to the first corner display area CDA1, respectively.

The second corner driving circuit CDRV2 is a corner driving circuit CDRVthat is electrically connected to the pixel circuit configured to drivethe corner pixels PXc, but is not electrically connected to the pixelcircuit configured to drive the front pixels PXf. The gate line GLconnected to the second corner driving circuit CDRV2 extends in adirection from the second corner driving circuit CDRV2 to the firstcorner display area CDA1, and does not extend in a direction toward thefront display area FDA.

The peripheral area PA may be arranged outside the display area DA. Inan embodiment, the peripheral area PA may be arranged outside the sidedisplay area SDA and outside the corner display area CDA. The peripheralarea PA may include a gate driving circuit GDRV and a terminal portionPDA.

The gate driving circuit GDRV may be configured to provide a controlsignal (e.g., a scan signal and/or an emission control signal) fordriving the front pixels PXf and the side pixels PXs. The gate drivingcircuit GDRV may be arranged at a right side of the second side displayarea SDA2 and/or at a left side of the third side display area SDA3. Thegate driving circuit GDRV may be connected to the gate line GL extendingin the x-direction.

The terminal portion PDA may be arranged at a lower side of the firstside display area SDA1. The terminal portion PDA is not covered by aninsulating layer and is exposed to be connected to a display circuitboard FPCB. A display driver 32 may be arranged or disposed on thedisplay circuit board FPCB.

The display driver 32 may generate a control signal to be transmitted tothe corner driving circuit CDRV and the gate driving circuit GDRV. Thedisplay driver 32 may further generate a data signal. The generated datasignal may be transmitted to the front pixels PXf, the side pixels PXs,and the corner pixels PXc through the fan-out wire FW and the data lineDL electrically connected to the fan-out wire FW. A front data line DLfmay extend in the y-direction to be electrically connected to the pixelcircuits configured to drive the front pixels PXf. A corner data lineDLc may be bent from the front display area FDA and may extend in adirection toward the corner display area CDA. The corner data line DLcmay be electrically connected to the pixel circuits configured to drivethe corner pixels PXc.

FIG. 4 is a schematic cross-sectional view of a part of the displaypanel 10, according to an embodiment. FIG. 4 corresponds to across-sectional view of the display panel 10 taken along line II-II′ ofFIG. 3B.

In an embodiment, as illustrated in FIG. 4, the display panel 10 mayinclude the corner display area CDA and the front display area FDA, andthe corner display area CDA may include the first corner display areaCDA1 and the second corner display area CDA2. The display panel 10 mayinclude the substrate 100 and a display layer DISL, a touchscreen layerTSL, and an optical functional layer OFL, which are arranged over thesubstrate 100.

The display layer DISL may include a circuit layer including thin-filmtransistors TFTf, TFTc, and TFTd, a display element layer includinglight-emitting elements EDf and EDc, which are display elements, and anencapsulation layer TFEL. Insulating layers IL and IL′ may be arrangedin the display layer DISL and may be between the substrate 100 and thedisplay layer DISL.

The substrate 100 may include at least one selected from variousmaterials such as glass, metal, or an organic material. In anembodiment, the substrate 100 may include a flexible material. In oneembodiment, for example, the substrate 100 may include ultra-thinflexible glass (e.g., a thickness of tens to hundreds of micrometers(μm)) or a polymer resin. In an embodiment where the substrate 100includes a polymer resin, the substrate 100 may include polyimide.Alternatively, the substrate 100 may include polyethersulfone,polyarylate, polyetherimide, polyethylene naphthalate, polyethyleneterephthalate (“PET”), polyphenylene sulfide, polycarbonate, cellulosetriacetate, and/or cellulose acetate propionate.

A front pixel circuit PCf and a front display element EDf electricallyconnected thereto may be arranged in the front display area FDA of thedisplay panel 10. The front pixel circuit PCf may include a frontthin-film transistor TFTf and may be configured to control lightemission of the front display element EDf.

Corner pixel circuits PCc and corner display elements EDc electricallyconnected thereto may be arranged in the first corner display area CDA1and the second corner display area CDA2 of the display panel 10. Eachcorner pixel circuit PCc may include a corner thin-film transistor TFTcand may be configured to control light emission of the corner displayelement EDc.

In an embodiment, the corner driving circuit CDRV may be furtherarranged in the second corner display area CDA2. The corner drivingcircuit CDRV includes a driving circuit thin-film transistor TFTd andmay be configured to provide a control signal (e.g., a scan signaland/or an emission control signal) to corner pixel circuits PCc arrangedin the corner display area CDA. The corner display elements EDc arrangedin the first corner display area CDA1 and the second corner display areaCDA2 may be arranged in a same pixel arrangement as each other or indifferent pixel arrangements from each other. In an embodiment, thecorner display element EDc arranged in the second corner display areaCDA2 may be arranged to overlap the corner driving circuit CDRV.

The front display element EDf and the corner display elements EDc, whichare display elements, may be easily damaged by moisture or oxygen fromthe outside, and thus may be covered and protected by the encapsulationlayer TFEL. The encapsulation layer TFEL may include at least oneorganic encapsulation layer and at least one inorganic encapsulationlayer. In one embodiment, for example, the encapsulation layer TFEL mayinclude a first inorganic encapsulation layer 131, an organicencapsulation layer 132, and a second inorganic encapsulation layer 133.

The first inorganic encapsulation layer 131 and the second inorganicencapsulation layer 133 may include silicon oxide, silicon nitride,and/or silicon trioxynitride. Because the first inorganic encapsulationlayer 131 is formed along a structure thereunder, an upper surfacethereof is not flat, and thus the organic encapsulation layer 132 isformed to cover the first inorganic encapsulation layer 131 so that theupper surface thereof is flat. The organic encapsulation layer 132 mayinclude at least one material selected from polyethylene terephthalate,polyethylene naphthalate, polycarbonate, polyimide, polyethylenesulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

The touchscreen layer TSL may obtain coordinate informationcorresponding to an external input, for example, a touch event. Thetouchscreen layer TSL may include a touch electrode and touch wiresconnected to the touch electrode. The touchscreen layer TSL may sense anexternal input by using a self-capacitance method or a mutualcapacitance method.

In an embodiment, the touchscreen layer TSL may be disposed or formed onthe encapsulation layer TFEL. Alternatively, the touchscreen layer TSLmay be separately formed over a touch substrate and then coupled ontothe encapsulation layer TFEL through an adhesive layer such as an OCA.In an embodiment, the touchscreen layer TSL may be directly formed onthe encapsulation layer TFEL, and in such an embodiment, the adhesivelayer may not be between the touchscreen layer TSL and the encapsulationlayer TFEL.

The optical functional layer OFL may include an anti-reflective layer.The anti-reflective layer may reduce the reflectance of light (externallight) incident from the outside toward the display apparatus 1. In anembodiment, the optical functional layer OFL may be a polarization film.In an alternative embodiment, the optical functional layer OFL may beprovided as a filter plate including a black matrix and color filters.

The display panel 10 may be a display panel including a light-emittingelement. The light-emitting element included in the display panel 10 maybe an organic light-emitting diode (“LED”), an inorganic LED, a microLED, or a quantum dot LED. Hereinafter, for convenience of description,embodiments where each of the pixels included in the display panel 10 isa light-emitting element including an organic LED will be described indetail.

FIG. 5 is a schematic cross-sectional view of a part of a display panel,according to an embodiment. FIG. 5 corresponds to a cross-sectional viewof the display panel 10 (see FIG. 3) taken along line III-Ill′ of FIG.3A.

Referring to FIG. 5, a front pixel circuit PCf including a thin-filmtransistor TFT and a storage capacitor Cst, and an organiclight-emitting diode OLED as a display element connected to the frontpixel circuit PCf may be arranged in the front display area FDA. Onefront subpixel may be implemented in an emission area EA of the organiclight-emitting diode OLED.

In an embodiment, the display panel 10 may include the substrate 100 andstacked elements arranged or disposed on the substrate 100. Hereinafter,a stacked structure of the display panel 10 will be described in detail.

The substrate 100 may include an insulating material such as glass,quartz, or a polymer resin. The substrate 100 may include a rigidsubstrate or a flexible substrate that is bendable, foldable, orrollable. In one embodiment, for example, the substrate 100 may have astructure in which an organic layer and an inorganic layer are stackedalternately one on another.

Referring to FIG. 5, a buffer layer 111 may be disposed on the substrate100. The buffer layer 111 may reduce or prevent penetration of foreignmaterials, moisture, or external air from a lower portion of thesubstrate 100 and may increase smoothness of an upper surface of thesubstrate 100. The buffer layer 111 may include an inorganic materialsuch as oxide or nitride, an organic material, or an organic/inorganiccomposite and may have a single-layered or multiple-layered structure ofan inorganic material and an organic material. A barrier layer (notillustrated) that blocks penetration of external air may be furtherincluded between the substrate 100 and the buffer layer 111. In anembodiment, the buffer layer 111 may include silicon oxide and/orsilicon nitride.

The thin-film transistor TFT may be arranged or disposed on the bufferlayer 111. The thin-film transistor TFT may include a semiconductorlayer Act, a gate electrode GE, a source electrode SE, and a drainelectrode DE. The thin-film transistor TFT may be connected to theorganic light-emitting diode OLED to drive the organic light-emittingdiode OLED. In an embodiment, as illustrated in the drawings, a top-gatetype thin-film transistor in which the gate electrode GE is arrangedover the semiconductor layer Act with a first gate insulating layer 112therebetween, but not being limited thereto. Alternatively, thethin-film transistor TFT may include a bottom-gate type thin-filmtransistor.

The semiconductor layer Act may be disposed on the buffer layer 111. Thesemiconductor layer Act may include a channel region, and a sourceregion and a drain region doped with impurities at both opposing sidesof the channel region. In such an embodiment, the impurities may includeN-type impurities or P-type impurities. In an embodiment, thesemiconductor layer Act may include polysilicon. In an alternativeembodiment, the semiconductor layer Act may include amorphous silicon.In another alternative embodiment, the semiconductor layer Act mayinclude an oxide of at least one selected from indium (In), gallium(Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium(Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). In anembodiment, the semiconductor layer Act may include a Zn oxide-basedmaterial, for example, Zn oxide, In—Zn oxide, Ga—In—Zn oxide, or thelike. In an embodiment, the semiconductor layer Act may be In—Ga—Zn—O(“IGZO”) semiconductor, In—Sn—Zn—O (“ITZO”) semiconductor, orIn—Ga—Sn—Zn—O (“IGTZO”) semiconductor including metal such as In, Ga,and Sn in ZnO.

The first gate insulating layer 112 may cover the semiconductor layerAct. The first gate insulating layer 112 may include an inorganicinsulating material such as silicon oxide, silicon nitride, siliconoxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafniumoxide. The first gate insulating layer 112 may have a single layerstructure or a multilayer structure, each layer including at least oneselected from the aforementioned inorganic insulating materials.

The gate electrode GE is arranged or disposed on the first gateinsulating layer 112 to overlap the semiconductor layer Act. In anembodiment, the gate electrode GE may overlap the channel region of thesemiconductor layer Act. The gate electrode GE may include at least oneselected from various conductive materials including molybdenum (Mo),aluminum (Al), copper (Cu), Ti, and the like and may have various layerstructures. In one embodiment, for example, the gate electrode GE mayinclude a Mo layer and an Al layer or may have a multi-layered structureof a Mo layer/an Al layer/a Mo layer. Alternatively, the gate electrodeGE may have a multi-layered structure including an ITO layer covering ametal material.

A second gate insulating layer 113 may be disposed or arranged on thefirst gate insulating layer 112 to cover the gate electrode GE. Thesecond gate insulating layer 113 may include an inorganic insulatingmaterial such as silicon oxide, silicon nitride, silicon oxynitride,aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. Thesecond gate insulating layer 113 may have a single layer structure or amultilayer structure, each layer including at least one selected fromthe aforementioned inorganic insulating materials.

An upper electrode CE2 of the storage capacitor Cst may be arranged ordisposed on the second gate insulating layer 113. The upper electrodeCE2 of the storage capacitor Cst may overlap the gate electrode GEthereunder. The gate electrode GE and the upper electrode CE2, whichoverlap each other with the second gate insulating layer 113therebetween, may form or collectively define the storage capacitor Cst.The gate electrode GE may be a lower electrode CE1 of the storagecapacitor Cst.

The upper electrode CE2 may include Al, platinum (Pt), palladium (Pd),silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd),iridium (Ir), Cr, calcium (Ca), Mo, Ti, tungsten (W), and/or Cu and mayhave a single layer structure or a multilayer structure, each layerincluding at least one selected from the aforementioned materials.

An interlayer insulating layer 115 may cover the upper electrode CE2 ofthe storage capacitor Cst. The interlayer insulating layer 115 mayinclude an inorganic insulating material such as silicon oxide, siliconnitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalumoxide, or hafnium oxide. The interlayer insulating layer 115 may have asingle layer structure or a multilayer structure, each layer includingat least one selected from the aforementioned inorganic insulatingmaterials.

The source electrode SE and the drain electrode DE may be arranged ordisposed on the interlayer insulating layer 115. Each of the sourceelectrode SE and the drain electrode DE may include a conductivematerial including Mo, Al, Cu, Ti, and the like and may have a singlelayer structure or a multilayer structure, each layer including at leastone selected from the aforementioned materials. In one embodiment, forexample, the source electrode SE and the drain electrode DE may includea Ti layer and an Al layer or may have a multi-layered structure of a Tilayer/an Al layer/a Ti layer. Alternatively, the source electrode SE andthe drain electrode DE may have a multi-layered structure including anITO layer covering a metal material.

The thin-film transistor TFT may be covered by a first organicinsulating layer 116. The first organic insulating layer 116 may coverthe source electrode SE and the drain electrode DE. A connectionelectrode CM and various wires WR, for example, a driving voltage lineor a data line, may be arranged or disposed on the first organicinsulating layer 116 and thus may be desired in high integration. Asecond organic insulating layer 117 may be arranged or disposed on thefirst organic insulating layer 116 to cover the connection electrode CMand the wires WR.

The first and second organic insulating layers 116 and 117 may eachinclude a flat upper surface so that an element arranged thereon may beflat. The first and second organic insulating layers 116 and 117 mayinclude a general-purpose polymer such as photosensitive polyimide,polyimide, polystyrene (“PS”), polycarbonate (“PC”), benzocyclobutene(“BCB”), or polymethylmethacrylate (“PMMA”), a polymer derivative havinga phenolic group, an acrylic polymer, an imide-based polymer, anarylether-based polymer, an amide-based polymer, a fluorine-basedpolymer, a p-xylene-based polymer, or a vinyl alcohol-based polymer. Inan embodiment, the first organic insulating layer 116 may include asiloxane-based organic material having high light transmittance andflatness, for example, hexamethyldisiloxane, octamethyltrisiloxane,decamethyltetrasiloxane, dodecamethylpentasiloxane, andpolydimethylsiloxane.

The organic light-emitting diode OLED may be arranged or disposed overthe second organic insulating layer 117. A first electrode 121 of theorganic light-emitting diode OLED may be connected to the front pixelcircuit PCf through the connection electrode CM arranged or disposed onthe first organic insulating layer 116.

The first electrode 121 may include a conductive oxide such as indiumtin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indiumoxide (In₂O₃), indium gallium oxide (“IGO”), or aluminum zinc oxide(“AZO”). The first electrode 121 may include a reflective layerincluding Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or any compoundthereof. In one embodiment, for example, the first electrode 121 mayhave a structure including layers including ITO, IZO, ZnO, or In₂O₃ overand/or under the reflective layer. In an embodiment, the first electrode121 may have a multi-layered structure of an ITO layer/an Ag layer/anITO layer.

A pixel-defining layer 119 may be arranged or disposed on the secondorganic insulating layer 117 to cover an edge of the first electrode121. A pixel opening OP may be defined through the pixel-defining layer119 to expose a central portion of the first electrode 121. A size andshape of the emission area EA of the organic light-emitting diode OLEDmay be defined by the pixel opening OP of the pixel-defining layer 119.

The pixel-defining layer 119 may prevent an electric arc or the likefrom occurring on the edge of the first electrode 121 by increasing adistance between the edge of the first electrode 121 and a secondelectrode 123 on the first electrode 121. In one embodiment, forexample, the pixel-defining layer 119 may include an organic insulatingmaterial such as polyimide, polyamide, an acrylic resin, BCB,hexamethyldisiloxane (“HMDSO”), and a phenolic resin and may be formedby a spin coating, etc.

An emission layer 122 b formed to correspond to the first electrode 121is disposed in the pixel opening OP of the pixel-defining layer 119. Theemission layer 122 b may include a polymer material or a low molecularweight material and may emit red, green, blue, or white light.

An intermediate layer 122 may be arranged or disposed on thepixel-defining layer 119, and the intermediate layer 122 may cover anupper surface of the first electrode 121 exposed by the pixel openingOP.

The intermediate layer 122 may include the emission layer 122 b. Theemission layer 122 b may include, for example, an organic material. Theemission layer 122 b may include a polymer organic material or a lowmolecular weight organic material that emits light having a certaincolor. The intermediate layer 122 may include a first common layer 122 aarranged or disposed under the emission layer 122 b and/or a secondcommon layer 122 c arranged or disposed on the emission layer 122 b.

The first common layer 122 a may have a single layer structure or amultilayer structure. In one embodiment, for example, where the firstcommon layer 122 a includes a polymer material, the first common layer122 a, which is a hole transport layer (“HTL”) that is a single-layeredstructure, may include poly-(3,4)-ethylene-dihydroxy thiophene (“PEDOT”)or polyaniline (“PANI”). In an embodiment where the first common layer122 a includes a low molecular weight material, the first common layer122 a may include a hole injection layer (“HIL”) and the HTL.

The second common layer 122 c may be optional or selectively omitted. Inone embodiment, for example, where the first common layer 122 a and theemission layer 122 b include a polymer material, the second common layer122 c may be provided or formed. The second common layer 122 c may havea single layer structure or a multilayer structure. The second commonlayer 122 c may include an electron transport layer (“ETL”) and/or anelectron injection layer (“EIL”).

The emission layer 122 b of the intermediate layer 122 may be arrangedfor each subpixel in the display area DA. The emission layer 122 b maybe disposed to overlap the pixel-defining layer 119, the pixel openingOP, and/or the first electrode 121. Each of the first and second commonlayers 122 a and 122 c of the intermediate layer 122 may be integrallyformed as a single unitary body over the subpixels.

The second electrode 123 may include a conductive material having a lowwork function. In one embodiment, for example, the second electrode 123may include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au,Ni, Nd, Ir, Cr, lithium (Li), Ca, or any alloy thereof. Alternatively,the second electrode 123 may further include a layer such as ITO, IZO,ZnO, or In₂O₃ on the (semi-)transparent layer including theaforementioned material. The second electrode 123 may be integrallyformed as a single unitary body to cover a plurality of first electrodes121 in the display area DA. The intermediate layer 122 and the secondelectrode 123 may be formed by a thermal evaporation method.

Because the aforementioned organic light-emitting diode OLED may beeasily damaged by external moisture, oxygen, or the like, the organiclight-emitting diode OLED may be covered and protected by theencapsulation layer TFEL. The encapsulation layer TFEL may include atleast one organic encapsulation layer and at least one inorganicencapsulation layer. In one embodiment, for example, as illustrated inFIG. 5, the encapsulation layer TFEL may include the first inorganicencapsulation layer 131, the organic encapsulation layer 132, and thesecond inorganic encapsulation layer 133.

The first inorganic encapsulation layer 131 may cover the secondelectrode 123. Other layers such as a capping layer (not illustrated)may be interposed between the first inorganic encapsulation layer 131and the second electrode 123. Because the first inorganic encapsulationlayer 131 is formed along a structure thereunder, an upper surfacethereof is not flat, and thus the organic encapsulation layer 132 isformed to cover the first inorganic encapsulation layer 131 so that theupper surface thereof is flat. The second inorganic encapsulation layer133 may cover the organic encapsulation layer 132.

The first and second inorganic encapsulation layers 131 and 133 mayinclude silicon oxide, silicon nitride, and/or silicon trioxynitride. Inan embodiment, the organic encapsulation layer 132 may include at leastone material selected from polyethylene terephthalate, polyethylenenaphthalate, polycarbonate, polyimide, polyethylene sulfonate,polyoxymethylene, polyarylate, and hexamethyldisiloxane. The organicencapsulation layer 132 may be formed by coating a monomer havingflowability and then curing a monomer layer by using light such as heator ultraviolet rays. Alternatively, the organic encapsulation layer 132may be formed by coating the aforementioned polymer-based material. Inan embodiment, each of the first inorganic encapsulation layer 131, theorganic encapsulation layer 132, and the second inorganic encapsulationlayer 133 may be integrally formed as a single unity body to cover thefront display area FDA.

In an embodiment, the side display area SDA and the corner display areaCDA may have a same stacked structure of the front display area FDAdescribed above.

FIG. 6A is an equivalent circuit diagram of a subpixel according to anembodiment, and FIG. 6B is an equivalent circuit diagram of the subpixelaccording to an alternative embodiment.

Referring to FIG. 6A, in an embodiment, a pixel circuit PC may beconnected to a light-emitting element ED to implement light emission ofsubpixels. The pixel circuit PC may include a driving thin-filmtransistor T1, a switching thin-film transistor T2, and a storagecapacitor Cst. The switching thin-film transistor T2 is connected to ascan line SL and a data line DL and may be configured to transmit a datasignal Dm to the driving thin-film transistor T1 in response to a scansignal Sn input through the scan line SL, such that the data signal Dmis input through the data line DL.

The storage capacitor Cst is connected to the switching thin-filmtransistor T2 and a driving voltage line PL and is configured to store avoltage corresponding to a difference between a voltage received fromthe switching thin-film transistor T2 and a driving voltage ELVDDsupplied to the driving voltage line PL.

The driving thin-film transistor T1 may be connected to the drivingvoltage line PL and the storage capacitor Cst and may control a drivingcurrent flowing from the driving voltage line PL to the light-emittingelement ED in response to a voltage value stored in the storagecapacitor Cst. The light-emitting element ED may emit light having aluminance corresponding to the driving current.

FIG. 6A illustrates an embodiment where the pixel circuit PC includestwo thin-film transistors T1 and T2 and a single storage capacitor Cst,but one or more embodiments are not limited thereto. In such anembodiment, the number of thin-film transistors and the number ofcapacitors included in the pixel circuit PC may be variously changedaccording to a design of the pixel circuit PC. In one alternativeembodiment, for example, the pixel circuit PC may further include threeor more thin-film transistors in addition to the two thin-filmtransistors described above. In such an embodiment, one or morecapacitors may be further included in addition to the storage capacitorCst described above.

In an alternative embodiment, referring to FIG. 6B, the pixel circuit PCmay include the driving thin-film transistor T1, the switching thin-filmtransistor T2, a compensation thin-film transistor T3, a firstinitialization thin-film transistor T4, an operation control thin-filmtransistor T5, an emission control thin-film transistor T6, and a secondinitialization thin-film transistor T7.

FIG. 6B illustrates an embodiment where each pixel circuit PC connectedto signal lines SL, SL−1, SL+1, EL, and DL, an initialization voltageline VL, and a driving voltage line PL, but one or more embodiments arenot limited thereto. In an alternative embodiment, at least one of thesignal lines SL, SL−1, SL+1, EL, and DL, and/or the initializationvoltage line VL may be shared by pixel circuits PC adjacent to eachother.

A drain electrode of the driving thin-film transistor T1 may beelectrically connected to the light-emitting element ED via the emissioncontrol thin-film transistor T6. The driving thin-film transistor T1receives a data signal Dm in response to a switching operation of theswitching thin-film transistor T2 and supplies a driving current to thelight-emitting element ED.

A gate electrode of the switching thin-film transistor T2 is connectedto the scan line SL, and a source electrode of the switching thin-filmtransistor T2 is connected to the data line DL. A drain electrode of theswitching thin-film transistor T2 may be connected to a source electrodeof the driving thin-film transistor T1 and the driving voltage line PLvia the operation control thin-film transistor T5.

The switching thin-film transistor T2 is turned on in response to thescan signal Sn received through the scan line SL and performs aswitching operation of transmitting the data signal Dm received throughthe data line DL to the source electrode of the driving thin-filmtransistor T1.

A gate electrode of the compensation thin-film transistor T3 may beconnected to the scan line SL. A source electrode of the compensationthin-film transistor T3 may be connected to a first electrode (e.g., ananode) of the light-emitting element ED via the emission controlthin-film transistor T6 while being connected to the drain electrode ofthe driving thin-film transistor T1. A drain electrode of thecompensation thin-film transistor T3 may be simultaneously connected toone of electrodes of the storage capacitor Cst, a source electrode ofthe first initialization thin-film transistor T4, and a gate electrodeof the driving thin-film transistor T1. The compensation thin-filmtransistor T3 is turned on in response to the scan signal Sn receivedthrough the scan line SL and connects the gate electrode and the drainelectrode of the driving thin-film transistor T1 to each other, so thatthe driving thin-film transistor T1 is diode-connected.

A gate electrode of the first initialization thin-film transistor T4 maybe connected to a previous scan line SL−1. A drain electrode of thefirst initialization thin-film transistor T4 may be connected to theinitialization voltage line VL. A source electrode of the firstinitialization thin-film transistor T4 may be simultaneously connectedto one of the electrodes of the storage capacitor Cst, the drainelectrode of the compensation thin-film transistor T3, and the gateelectrode of the driving thin-film transistor T1. The firstinitialization thin-film transistor T4 may be turned on in response to aprevious scan signal Sn−1 transmitted through the previous scan lineSL−1 and may perform an initialization operation of initializing avoltage of the gate electrode of the driving thin-film transistor T1 bytransmitting an initialization voltage Vint to the gate electrode of thedriving thin-film transistor T1.

A gate electrode of the operation control thin-film transistor T5 may beconnected to an emission control line EL. A source electrode of theoperation control thin-film transistor T5 may be connected to thedriving voltage line PL. A drain electrode of the operation controlthin-film transistor T5 is connected to the source electrode of thedriving thin-film transistor T1 and the drain electrode of the switchingthin-film transistor T2.

A gate electrode of the emission control thin-film transistor T6 may beconnected to the emission control line EL. A source electrode of theemission control thin-film transistor T6 may be connected to the drainelectrode of the driving thin-film transistor T1 and the sourceelectrode of the compensation thin-film transistor T3. A drain electrodeof the emission control thin-film transistor T6 may be electricallyconnected to the first electrode of the light-emitting element ED. Theoperation control thin-film transistor T5 and the emission controlthin-film transistor T6 are simultaneously turned on in response to anemission control signal En received through the emission control line ELand are configured to transmit the driving voltage ELVDD to thelight-emitting element ED, so that a driving current flows through thelight-emitting element ED.

A gate electrode of the second initialization thin-film transistor T7may be connected to a next scan line SL+1. A source electrode of thesecond initialization thin-film transistor T7 may be connected to thefirst electrode of the light-emitting element ED. A drain electrode ofthe second initialization thin-film transistor T7 may be connected tothe initialization voltage line VL. The second initialization thin-filmtransistor T7 is turned on in response to a next scan signal Sn+1received through the next scan line SL+1 and may initialize the firstelectrode of the light-emitting element ED.

FIG. 6B illustrates an embodiment where the first initializationthin-film transistor T4 and the second initialization thin-filmtransistor T7 are connected to the previous scan line SL−1 and the nextscan line SL+1, respectively, but one or more embodiments are notlimited thereto. In an alternative embodiment, the first initializationthin-film transistor T4 and the second initialization thin-filmtransistor T7 may all be connected to the previous scan line SL−1 andmay be driven based on the previous scan signal Sn−1.

The other of the electrodes of the storage capacitor Cst may beconnected to the driving voltage line PL. One of the electrodes of thestorage capacitor Cst may be simultaneously connected to the gateelectrode of the driving thin-film transistor T1, the drain electrode ofthe compensation thin-film transistor T3, and the source electrode ofthe first initialization thin-film transistor T4.

A second electrode (e.g., a cathode) of the light-emitting element EDreceives a common voltage ELVSS. The light-emitting element ED receivesa driving current from the driving thin-film transistor T1 and emitslight.

The pixel circuit PC is not limited to the number of thin-filmtransistors, the number of storage capacitors, and the circuit designsdescribed above with reference to FIGS. 6A and 6B. The number ofthin-film transistors, the number of storage capacitors, and the circuitdesigns may vary.

The pixel circuits PC configured to drive subpixels arranged in each ofthe front display area FDA, the side display area SDA, and the cornerdisplay area CDA may be provided identically or differently from eachother. In an embodiment, the pixel circuit PC configured to drive thesubpixels arranged in each of the front display area FDA, the sidedisplay area SDA, and the corner display area CDA may be provided as thepixel circuit PC illustrated in FIG. 6B. In an alternative embodiment,the pixel circuit PC configured to drive the subpixels arranged in atleast some of the front display area FDA, the side display area SDA, andthe corner display area CDA may employ the pixel circuit PC illustratedin FIG. 6B, and the pixel circuit PC configured to drive the subpixelsarranged in the remaining part may employ the pixel circuit PCillustrated in FIG. 6A.

FIG. 7 is an enlarged schematic plan view of a part of the displaypanel, according to an embodiment. In detail, FIG. 7 illustrates anenlarged view of the corner display area CDA of the display panel, inwhich the display panel is not bent and is unfolded.

As illustrated in FIG. 7, an embodiment of the display panel 10 mayinclude a plurality of extension portions LP and a plurality of cutoutportions V that are arranged to correspond to the corner display areaCDA. The extension portions LP are areas extending in a direction awayfrom the front display area FDA. The cutout portions V may be areasdefined between the extension portions LP and may be through portionsdefined through the display panel 10.

Respective ends of the extension portions LP may be apart from eachother with certain gaps. Empty spaces may be defined or formed betweenthe extension portions LP due to the gaps, and may correspond to thecutout portions V, respectively. The gaps between the extension portionsLP may vary. In an embodiment, as illustrated in FIG. 7, the gap betweenthe extension portions LP in the front display area FDA may increase asmoving in a direction away from the front display area FDA. In such anembodiment, the extension portions LP may be radially arranged. In analternative embodiment, the gaps between the extension portions LP maynot vary and be constant. In such an embodiment, the extension portionsLP may be arranged in parallel to each other.

The extension portions LP may be connected at a portion adjacent to thefront display area FDA. In an embodiment, as illustrated in FIG. 7, theextension portions LP may extend from the second corner display areaCDA2 in a direction away from the front display area FDA. In analternative embodiment, the extension portions LP may extend from thefront display area FDA in a direction away from the front display areaFDA. In an embodiment, the extension portions LP may extend to theperipheral area PA. In such an embodiment, at least part of the ends ofthe extension portions LP may overlap the peripheral area PA.

Extended lengths (or lengths in extending directions) of the extensionportions LP may be different from each other. The extended lengths ofthe extension portions LP may be different from each other depending ona distance by which the extension portions LP are apart from a centralportion of the corner display area CDA. In one embodiment, for example,among the extension portions LP, extension portions LP positioned at thecentral portion of the corner display area CDA may have a length in adirection away from the front display area FDA longer than that of theother extension portions LP. The extended lengths of extension portionsLP may decrease as the extension portions LP are arranged farther fromthe central portion of the corner display area CDA.

Each of the cutout portions V may be defined through the display panel10 from a front surface to a bottom surface of the display panel 10.Each of the cutout portions V may improve flexibility of the displaypanel 10. In such an embodiment, when external force (e.g., force suchas bending, bending, or pulling) is applied to the display panel 10,shapes of the cutout portions V are changed, and thus, stress occurrencewhile the display panel 10 is transformed is reduced, and accordingly,durability of the display panel 10 may be improved.

When external force is applied to the display panel 10, areas or shapesof the cutout portions V may be changed, and positions of the extensionportions LP may be changed. In one embodiment, for example, when forceof bending edges of the display panel 10 and corner portionstherebetween is applied, the gaps between the extension portions LP arereduced, and thus, the areas of the cutout portions V may be reduced,and the extension portions LP adjacent to each other may contact eachother.

In an embodiment, as described above, when external force is applied tothe display panel 10, the gaps between the extension portions LP, theareas of the cutout portions V, etc. may be changed, and the shapes ofthe extension portions LP may not be changed. In such an embodiment, apixel circuit, a display element, and the like may be arranged in eachof the extension portions LP, and even when external force is applied tothe display panel 10, the shapes of the extension portions LP are notchanged, and thus, the pixel circuit, the display element, and the likearranged in each of the extension portions LP may be protected.

In such an embodiment, where the shapes of the extension portions LP maynot be changed when external force is applied to the display panel 10,the corner pixels PXc may be stably arranged in the corner display areaCDA of the display panel 10. Accordingly, a display area in which animage is implemented may be expanded from the front display area FDA andthe side display area SDA to the corner display area CDA. The cornerpixels PXc arranged in the extension portions LP may be arranged to beapart from each other along an extension direction of the extensionportions LP.

FIG. 8 is an enlarged schematic plan view of a part of the displaypanel, according to an embodiment. In detail, FIG. 8 illustrates anenlarged view of the corner display area CDA of the display panel, inwhich the display panel is not bent and is unfolded.

As illustrated in FIG. 8, an embodiment of the display panel may includea display area and the peripheral area PA. The display area may includea front display area FDA, a first side display area SDA1 connected tothe front display area FDA in a downward direction (e.g., a −ydirection), a third side display area SDA3 connected to the frontdisplay area FDA in a left direction (e.g., a −x direction), and acorner display area CDA between the first side display area SDA1 and thethird side display area SDA3 to surround at least part of the frontdisplay area FDA. In such an embodiment, the corner display area CDA mayinclude the first corner display area CDA1 and the second corner displayarea CDA2 between the front display area FDA and the first cornerdisplay area CDA1.

Gate lines GL extending in the x-direction and data lines DL extendingin the y-direction are arranged in the front display area FDA and theside display areas SDA1 and SDA3.

A voltage line VWL may be arranged in the second corner display areaCDA2. In an embodiment, the voltage line VWL may extend in an extensiondirection of the second corner display area CDA2. The voltage line VWLmay be the initialization voltage line VL (see FIG. 6B) and/or a commonvoltage line. The initialization voltage Vint (see FIG. 6B) and/or thecommon voltage ELVSS (see FIG. 6B) may be applied to the voltage lineVWL. The voltage line VWL may be electrically connected to a cornervoltage line CWLc arranged in the first corner display area CDA1.

A data connection line DCL may be arranged in the second corner displayarea CDA2. The data connection line DCL may be configured toelectrically connect the data line DL arranged in the front display areaFDA or the side display area SDA to the corner data line CWLa arrangedin the first corner display area CDA1. In an embodiment, the dataconnection line DCL may be arranged or disposed in or directly on adifferent layer from the data line DL and the corner data line CWLa. Insuch an embodiment, the data connection line DCL may be electricallyconnected to the data connection line DCL, the data line DL, and thecorner data line CWLa through a contact hole defined in an insulatinglayer provided between the data connection line DCL, the data line DL,and the corner data line CWLa. In an alternative embodiment, the dataconnection line DCL may be omitted, and the data line DL and the cornerdata line CWLa may be integrally formed as a single unitary body.

Corner driving circuits CDRV may be arranged in the second cornerdisplay area CDA2. The corner driving circuits CDRV may be arranged in adirection in which the second corner display area CDA2 extends.

The corner driving circuits CDRV arranged in the second corner displayarea CDA2 may include the first corner driving circuit CDRV1 and thesecond corner driving circuit CDRV2. The first corner driving circuitCDRV1 is a corner driving circuit CDRV that is electrically connected toboth of the pixel circuit configured to drive the corner pixels PXc andthe pixel circuit configured to drive the front pixels PXf. The gateline GL connected to the first corner driving circuit CDRV1 may extendin a direction from both opposing sides of the first corner drivingcircuit CDRV1 to the front display area FDA and to the first cornerdisplay area CDA1, respectively. The second corner driving circuit CDRV2is a corner driving circuit CDRV that is electrically connected to thepixel circuit configured to drive the corner pixels PXc (see FIG. 7),but is not electrically connected to the pixel circuit configured todrive the front pixels PXf (see FIG. 7). The gate line GL connected tothe second corner driving circuit CDRV2 extends in a direction from thesecond corner driving circuit CDRV2 to the first corner display areaCDA1, and does not extend in a direction toward the front display areaFDA.

In embodiments, the arrangement method of the first corner drivingcircuit CDRV1 and the second corner driving circuit CDRV2 are notparticularly limited. In an embodiment, as shown in FIG. 8, the firstcorner driving circuit CDRV1 and the second corner driving circuit CDRV2are alternately arranged with each other, but one or more embodimentsare not limited thereto. In one alternative embodiment, for example,first corner driving circuits CDRV1 may be arranged to correspond to thegate line GL, and second corner driving circuits CDRV2 may be arrangedconsidering a space between the first corner driving circuits CDRV1. Inan embodiment, the number of second corner driving circuits CDRV2between two adjacent first corner driving circuits CDRV1 may not beconstant and may be variously changed or modified.

At least some of the voltage line VWL, the data connection line DCL, thecorner driving circuit CDRV, and/or corner pixels arranged in the secondcorner display area CDA2 may be arranged to overlap each other.

The first corner display area CDA1 may include the extension portions LPextending in a direction away from the front display area FDA. In anembodiment, the extension portions LP may extend from the second cornerdisplay area CDA2 to the peripheral area PA, and the cutout portions Vmay be defined between the extension portions LP adjacent to each other.

In each of the extension portions LP, the corner pixels may be arrangedto be apart from each other in a direction in which the extensionportions LP extend. In an embodiment, the corner pixels may be arrangedonly in an area overlapping the corner display area CDA and may not bearranged in the peripheral area PA. In such an embodiment, the cornerpixels are not arranged in an area overlapping the peripheral area PA ofthe extension portions LP, but are arranged only in an area overlappingthe corner display area CDA of the extension portions LP.

Corner lines CWLa, CWLb, and CWLc may be arranged in each of theextension portions LP. Each of the corner lines CWLa, CWLb, and CWLc maybe arranged in each of the extension portions LP and may extend in adirection in which each of the extension portions LP extends. The cornerlines CWLa, CWLb, and CWLc may include the corner data line CWLa, acorner gate line CWLb, and the corner voltage line CWLc.

One end (or an end) of the corner data line CWLa may be electricallyconnected to the data line DL. In an embodiment, as described above, thecorner data line CWLa may be electrically connected to the data line DLthrough the data connection line DCL. In an alternative embodiment, thedata line DL and the corner data line CWLa may be integrally formed as asingle unitary body. The corner data line CWLa may overlap at least someof the corner pixels arranged in the corner display area CDA. In oneembodiment, for example, the corner data line CWLa may extend along eachof the extension portions LP and may overlap the corner pixels arrangedat a central portion of each of the extension portions LP. In anembodiment, the corner data line CWLa may be electrically connected tothe corner pixels arranged in the corner display area CDA and may beconfigured to transmit a data signal from the data line DL to the cornerpixels.

One end (or an end) of the corner gate line CWLb may be electricallyconnected to the gate line GL. In an embodiment, the corner gate lineCWLb and the gate line GL may be integrally formed as a single unitarybody. The corner gate line CWLb may extend along each of the extensionportions LP at an edge of each of the extension portions LP. In anembodiment, the corner gate line CWLb may be arranged at one side ofeach of the corner pixels arranged at the central portion of each of theextension portions LP. In an embodiment, the corner gate line CWLb,which is a corner signal line, may be electrically connected to thecorner pixels arranged in the corner display area CDA, and may beconfigured to transmit a gate signal (e.g., a scan signal and/or anemission control signal) from the gate line GL to the corner pixels.

One end (or an end) of the corner voltage line CWLc may be electricallyconnected to the voltage line VWL. In an embodiment, the corner voltageline CWLc and the voltage line VWL may be integrally formed as a singleunitary body. The corner voltage line CWLc may extend along each of theextension portions LP at the edge of each of the extension portions LP.In an embodiment, the corner voltage line CWLc may be arranged at theother side of each of the corner pixels arranged at the central portionof each of the extension portions LP. Here, the “other side” refers toan opposite side to the side where the aforementioned corner gate lineCWLb is arranged. The corner voltage line CWLc may be electricallyconnected to the corner pixels arranged in the corner display area CDA,and may be configured to transmit the initialization voltage Vint (seeFIG. 6B) and/or the common voltage ELVSS (see FIG. 6B) from the voltageline VWL to the corner pixels.

A load portion 400 may be selectively arranged in only some of theextension portions LP. In an embodiment, the extension portions LP mayinclude first extension portions LP1 and second extension portions LP2.In such an embodiment, the first extension portions LP1 refer toextension portions LP where the load portion 400 is not arranged amongthe extension portions LP, and the second extension portions LP2 referto extension portions LP where the load portion 400 is arranged amongthe extension portions LP.

The corner pixels electrically connected to the first corner drivingcircuit CDRV1 are arranged in the first extension portions LP1 in anextension direction of the first extension portions LP1. One end (or anend) of the corner gate line CWLb arranged in each of the firstextension portions LP1 is electrically connected to the first cornerdriving circuit CDRV1. One end (or an end) of the corner voltage lineCWLc arranged in each of the first extension portions LP1 iselectrically connected to the voltage line VWL. In an embodiment, theload portion 400 is not arranged in the first extension portions LP1,and thus the corner gate line CWLb and the corner voltage line CWLcarranged in the first extension portions LP1 are not electricallyconnected to the load portion 400.

The corner pixels electrically connected to the second corner drivingcircuit CDRV2 are arranged in the second extension portions LP2 along anextension direction of the second extension portions LP2. One end (or anend) of the corner gate line CWLb arranged in each of the secondextension portions LP2 is electrically connected to the second cornerdriving circuit CDRV2, and the other end (or another end or opposingend) of the corner gate line CWLb is electrically connected to the loadportion 400. One end (or an end) of the corner voltage line CWLcarranged in each of the second extension portions LP2 is electricallyconnected to the voltage line VWL, and the other end (or another end oropposing end) of the corner voltage line CWLc is electrically connectedto the load portion 400. Accordingly, the load portion 400 arranged ineach of the second extension portions LP2 may be electrically connectedto the second corner driving circuit CDRV2 through the corner gate lineCWLb arranged in each of the second extension portions LP2 and may beelectrically connected to the voltage line VWL through the cornervoltage line CWLc arranged in each of the second extension portions LP2.

The load portion 400 may stabilize the corner driving circuit CDRV. Inan embodiment, unlike the first corner driving circuit CDRV1 that iselectrically connected to both of the pixel circuit configured to drivethe corner pixels PXc and the pixel circuit configured to drive thefront pixels PXf, the load portion 400 may stabilize the second cornerdriving circuit CDRV2 that is electrically connected to the pixelcircuit configured to drive the corner pixels PXc but is notelectrically connected to the pixel circuit configured to drive thefront pixels PXf. In such an embodiment, because the second cornerdriving circuit CDRV2 is not electrically connected to the pixel circuitconfigured to drive the front pixels PXf, an active load of the secondcorner driving circuit CDRV2 is relatively smaller than that of thefirst corner driving circuit CDRV1. Accordingly, the second cornerdriving circuit CDRV2 is relatively greatly influenced by switching thatoccurs in another element when a signal is changed, that is, when avoltage is applied, so that a ripple may occur, thereby degradingdisplay quality.

In an embodiment of the invention, the display panel includes the loadportion 400 that is electrically connected to the second corner drivingcircuit CDRV2 to provide an additional load, thereby effectivelypreventing ripples from occurring in the second corner driving circuitCDRV2. In one embodiment, for example, the load portion 400 may be adecoupling capacitor electrically connected to the second corner drivingcircuit CDRV2. A detailed structure of the load portion 400 will bedescribed below with reference to FIGS. 11 to 13.

In such an embodiment, the load portion 400 may be arranged in an areaoverlapping the peripheral area PA of the second extension portions LP2.In such an embodiment, because the load portion 400 is arranged in theperipheral area PA, which is a non-display area in which an image is notdisplayed, an additional dead space may not be generated due to thearrangement of the load portion 400.

FIG. 9 is a schematic plan view of some of extension portions, accordingto an embodiment, and FIG. 10 is a schematic plan view of some of theextension portions, according to an alternative embodiment. In detail,FIGS. 9 and 10 are enlarged schematic plan views of first and secondextension portions LP1 and LP2 which are arranged adjacent to eachother. Hereinafter, the same or like reference numerals in the drawingsmay refer to the same or like elements as those described above, andthus, any repetitive detailed descriptions thereof will be omitted orsimplified for conciseness.

In an embodiment, as illustrated in FIG. 9, the corner pixels PXc may bearranged in an extension direction of each of the first and secondextension portions LP1 and LP2 at a portion where each of the first andsecond extension portions LP1 and LP2 overlaps the first corner displayarea CDA1. In such an embodiment, the corner gate line CWLb is arrangedalong each of the first and second extension portions LP1 and LP2 on oneside of the corner pixels PXc arranged or disposed in each of the firstand second extension portions LP1 and LP2, and the corner voltage lineCWLc is arranged along each of the first and second extension portionsLP1 and LP2 on the other side of the corner pixels PXc.

A connection portion CECNP may be arranged in an area adjacent to an endof each of the first and second extension portions LP1 and LP2. Theconnection portion CECNP may electrically connect the corner voltageline CWLc to the second electrode 123 (see FIG. 5) of the corner pixelsPXc. The connection portion CECNP will be described in greater detailbelow with reference to FIGS. 11 and 12.

In an embodiment, the load portion 400 may be arranged at an end of anarray of the corner pixels PXc arranged in the second extension portionLP2. In such an embodiment, the load portion 400 may not be arranged inthe first extension portion LP1.

One end (or an end) of the corner gate line CWLb arranged in the secondextension portion LP2 is electrically connected to the second cornerdriving circuit CDRV2, and the other end (or another end or opposingend) of the corner gate line CWLb is electrically connected to the loadportion 400. In an embodiment, the corner gate line CWLb and any one ofconductive layers of the load portion 400 may be integrally formed as asingle unitary body. One end (or an end) of the corner voltage line CWLcarranged in the second extension portion LP2 is electrically connectedto the voltage line VWL, and the other end (or another end or opposingend) of the corner voltage line CWLc is electrically connected to theload portion 400. In an embodiment, the corner voltage line CWLc and theload portion 400 may be electrically connected to each other through acontact hole PCNT defined in an insulating layer therebetween.

The number of load portions 400 arranged in the second extension portionLP2 is not limited and may be variously modified according to a design.

In an embodiment, as illustrated in FIG. 9, the load portion 400 may bearranged by one in each second extension portion LP2. In such anembodiment, a single second corner driving circuit CDRV2 may be arrangedto correspond to each second extension portion LP2.

In an alternative embodiment, as illustrated in FIG. 10, two loadportions 400 may be arranged in each second extension portion LP2. Insuch an embodiment, the two second corner driving circuits CDRV2 may bearranged to correspond to each second extension portion LP2, and thecorner gate line CWLb and the corner voltage line CWLc may be arrangedat one side and the other side of the corner pixels PXc, respectively.One of the two load portions 400 may be electrically connected to eachof the second corner driving circuit CDRV2 and the voltage line VWLthrough the corner gate line CWLb and the corner voltage line CWLcarranged at one side of the corner pixels PXc, and the other of the twoload portions 400 may be electrically connected to each of the secondcorner driving circuit CDRV2 and the voltage line VWL through the cornergate line CWLb and the corner voltage line CWLc arranged at the otherside of the corner pixels PXc. In an embodiment, the corner voltage lineCWLc arranged at each of one side and the other side of each of thecorner pixels PXc may be connected at the end of the array the cornerpixels PXc to be integrally formed as a single unitary body, and mayoverlap, and be electrically connected to, at least part of each of theload portions 400.

In another alternative embodiment, three load portions 400 may bearranged in each second extension portion LP2.

In such embodiments, a shape and area of the load portion 400 arrangedin the second extension portion LP2 may also be variously modified tohave a desired or predetermined load according to a design.

In an embodiment, when viewed in a direction perpendicular to thesubstrate 100 (see FIG. 5), that is, when viewed in a plan view, theshape of the load portion 400 may be a polygon, a polygon having atleast one side curved, a circle, an ellipse, or a sector shape.

In an embodiment, when viewed in a direction perpendicular to thesubstrate 100 (see FIG. 5), that is, when viewed in a plan view, a shapeof an outer edge of the load portion 400 may correspond to (e.g., be thesame as) a shape of an outer edge of the second extension portion LP2where the load portion 400 is arranged. In one embodiment, for example,when the outer edge of the second extension portion LP2 is a curvehaving a certain curvature, the outer edge of the load portion 400 maybe a curve having the same curvature as the outer edge of the secondextension portion LP2.

FIG. 11 is a schematic cross-sectional view of a part of an extensionportion, according to an embodiment, FIG. 12 is a schematiccross-sectional view of a part of the extension portion, according to analternative embodiment, and FIG. 13 is a schematic cross-sectional viewof a part of a load portion, according to an embodiment.

In detail, FIGS. 11 and 12 correspond to cross-sectional views of thedisplay panel taken along line IV-IV′ of FIG. 9, and FIG. 13 correspondsto a cross-sectional view of the display panel taken along line V-V ofFIG. 9. Hereinafter, the same or like reference numerals in the drawingsmay refer to the same or like elements as those described above, andthus, any repetitive detailed descriptions thereof will be omitted orsimplified for conciseness.

Referring to FIGS. 11 and 12, an embodiment of the display panelincludes the substrate 100 including the first corner display area CDA1arranged at a corner of the display panel and the peripheral area PAarranged outside the first corner display area CDA1.

In an embodiment, the corner pixel circuit PCc and a corner organiclight-emitting diode COLED that is arranged or disposed on the cornerpixel circuit PCc and electrically connected to the corner pixel circuitPCc may be positioned in the first corner display area CDA1.

A first groove G1 and a second groove G2, the connection portion CECNP,and the load portion 400 may be positioned in the peripheral area PA.FIGS. 11 and 12 illustrates an embodiment where the connection portionCECNP is arranged further outside than the load portion 400, but one ormore embodiments are not limited thereto.

A first corner inorganic pattern layer CPVX1 may be between the secondorganic insulating layer 117 and the corner organic light-emitting diodeCOLED. A second corner inorganic pattern layer CPVX2 may be apart fromthe first corner inorganic pattern layer CPVX1 on the second organicinsulating layer 117 with the first groove G1 therebetween. The secondcorner inorganic pattern layer CPVX2 may include an outer inorganicpattern layer CPVX2-1 and an inner inorganic pattern layer CPVX2-2,which are apart from each other. Each of the first corner inorganicpattern layer CPVX1 and the second corner inorganic pattern layer CPVX2may have a protruding tip PT protruding toward a center of each of thefirst groove G1 and the second groove G2. The protruding tips PT may beformed before the intermediate layer 122 and the second electrode 123are formed, and the intermediate layer 122 and/or the second electrode123 may be disconnected by the protruding tips PT.

The connection portion CECNP may include a pattern electrode 211P and aconnection line CL. The pattern electrode 211P on the second organicinsulating layer 117 may contact the connection line CL on the firstorganic insulating layer 116 through an opening defined in the secondorganic insulating layer 117. In an embodiment, the connection line CLmay be electrically connected to the voltage line VWL (see FIG. 9). Theinitialization voltage Vint (see FIG. 6B) and/or the common voltageELVSS (see FIG. 6B) may be applied from the voltage line VWL to thesecond electrode 123 through the connection portion CECNP.

The load portion 400 may be positioned in the peripheral area PA and maybe arranged further outside than the corner pixel circuit PCc. The loadportion 400 may include a plurality of conductive layers overlappingeach other. The conductive layers overlapping each other function as acapacitor to have a preset electric capacitance. The load portion 400may provide a decoupling effect to the second corner driving circuitCDRV2 (see FIG. 9) through the electric capacitance. In such anembodiment, the electric capacitance of the load portion 400 may bevariously modified to provide a desired or predetermined load accordingto a design.

The number, layer structure, and material of the conductive layersincluded in the load portion 400 are not limited and may be variouslymodified to have a desired or predetermined load according to a design.In an embodiment, the other end of the aforementioned corner gate lineCWLb (see FIG. 9) may be electrically connected to the lowermost layeramong the conductive layers included in the load portion 400, and theother end of the corner voltage line CWLc (see FIG. 9) may beelectrically connected to the uppermost layer among the conductivelayers included in the load portion 400.

In an embodiment, as illustrated in FIG. 11, the load portion 400 mayinclude a first conductive layer 400 a and a second conductive layer 400b that is positioned on the first conductive layer 400 a and overlapsthe first conductive layer 400 a. In such an embodiment, the other endof the corner gate line CWLb may be electrically connected to the firstconductive layer 400 a, and the other end of the corner voltage lineCWLc may be electrically connected to the second conductive layer 400 b.

The first conductive layer 400 a and a gate electrode GE of any one ofthin-film transistors TFT of the corner pixel circuit PCc and/or thelower electrode CE1 of the storage capacitor Cst may have a same layerstructure as each other and include a same material as each other. In anembodiment, the first conductive layer 400 a may be positioned on thefirst gate insulating layer 112. The first conductive layer 400 a mayinclude at least one selected from various conductive materialsincluding Mo, Al, Cu, Ti, and the like and may have one of various layerstructures. In one embodiment, for example, the first conductive layer400 a may include a Mo layer and an Al layer or may have a multi-layeredstructure of a Mo layer/an Al layer/a Mo layer.

The second conductive layer 400 b and an upper electrode CE2 of any oneof storage capacitors Cst of the corner pixel circuit PCc may have asame layer structure as each other and include a same material as eachother. In an embodiment, the second conductive layer 400 b may bepositioned on the second gate insulating layer 113. The secondconductive layer 400 b may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir,Cr, Ca, Mo, Ti, W, and/or Cu and may have a single layer structure or amultilayer structure, each layer including at least one selected fromthe aforementioned material.

In an alternative embodiment, when the load portion 400 includes thefirst conductive layer 400 a and the second conductive layer 400 b,unlike FIG. 11, the first conductive layer 400 a and any one of thesemiconductor layer Act, the gate electrode GE, the lower electrode CE1,and the upper electrode CE2 may have the same layer structure andinclude the same material, and the second conductive layer 400 b and anyone of the gate electrode GE, the lower electrode CE1, the upperelectrode CE2, the source electrode SE, and the drain electrode DE mayhave a same layer structure as each other and include a same material aseach other.

In another alternative embodiment, as illustrated in FIG. 12, the loadportion 400 may include the first conductive layer 400 a, the secondconductive layer 400 b that is arranged or disposed on the firstconductive layer 400 a and overlaps the first conductive layer 400 a,and a third conductive layer 400 c that is arranged or disposed on thesecond conductive layer 400 b and overlaps the second conductive layer400 b. In such an embodiment, the other end of the corner gate line CWLbmay be electrically connected to the first conductive layer 400 a, andthe other end of the corner voltage line CWLc may be electricallyconnected to the third conductive layer 400 c.

The first conductive layer 400 a and a semiconductor layer Act of anyone of the thin-film transistors TFT of the corner pixel circuit PCc mayhave a same layer structure as each other and include a same material aseach other. In an embodiment, the first conductive layer 400 a may bepositioned on the buffer layer 111. In an embodiment, the firstconductive layer 400 a may include polysilicon or amorphous silicon. Inan alternative embodiment, the first conductive layer 400 a may includean oxide of at least one selected from In, Ga, Sn, Zr, V, Hf, Cd, Ge,Cr, Ti, and Zn.

The second conductive layer 400 b and a gate electrode GE of any one ofthe thin-film transistors TFT of the corner pixel circuit PCc and/or thelower electrode CE1 of the storage capacitor Cst may have a same layerstructure as each other and include a same material as each other. In anembodiment, the second conductive layer 400 b may be positioned on thefirst gate insulating layer 112. In an embodiment, the second conductivelayer 400 b may include at least one selected from various conductivematerials including Mo, Al, Cu, Ti, and the like and may have one ofvarious layer structures. In one embodiment, for example, the secondconductive layer 400 b may include a Mo layer and an Al layer or mayhave a multi-layered structure of a Mo layer/an Al layer/a Mo layer.

The third conductive layer 400 c and an upper electrode CE2 of any oneof the storage capacitors Cst of the corner pixel circuit PCc may have asame layer structure as each other and include a same material as eachother. In an embodiment, the third conductive layer 400 c may bepositioned on the second gate insulating layer 113. The third conductivelayer 400 c may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo,Ti, W, and/or Cu and may have a single layer structure or a multilayerstructure, each layer including at least one selected from theaforementioned material.

In another alternative embodiment, where the load portion 400 includesthe first conductive layer 400 a, the second conductive layer 400 b, andthe third conductive layer 400 c, unlike FIG. 12, the first conductivelayer 400 a and any one of the semiconductor layer Act, the gateelectrode GE, and the lower electrode CE1 may have a same layerstructure as each other and include a same material as each other, thesecond conductive layer 400 b and any one of the gate electrode GE, thelower electrode CE1, and the upper electrode CE2 may have a same layerstructure as each other and include a same material as each other, andthe third conductive layer 400 c and any one of the upper electrode CE2,the source electrode SE, and the drain electrode DE may have a samelayer structure as each other and include a same material as each other.

In an embodiment, the uppermost layer of the conductive layers includedin the load portion 400 may be electrically connected to the cornervoltage line CWLc through the contact hole PCNT. In an embodiment, asshow in FIG. 13, where the load portion 400 includes the firstconductive layer 400 a and the second conductive layer 400 b, the secondconductive layer 400 b, which is the uppermost layer, is electricallyconnected to the corner voltage line CWLc. In such an embodiment, thesecond conductive layer 400 b and the corner voltage line CWLc may beelectrically connected through the contact hole PCNT defined in theinterlayer insulating layer 115. In such embodiments described above,the uppermost layer of the conductive layers included in the loadportion 400 may be electrically connected to the corner voltage lineCWLc through the contact hole PCNT defined in the insulating layer(s)therebetween.

Herein, embodiments of the display panel and the display apparatus havebeen described in detail, but the invention should not be construed asbeing limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete and will fully convey the concept of the invention to thoseskilled in the art. For example, methods of manufacturing the displaypanel and the display apparatus will also fall within the scope of thedisclosure.

According to embodiments as described above, a display panel, in which adisplay area is expended to display an image even on side areas and/orcorner areas, and a display apparatus including the display panel may beimplemented. However, the scope of the disclosure is not limited tothese effects.

While the invention has been particularly shown and described withreference to embodiments thereof, it will be understood by those ofordinary skill in the art that various changes in form and details maybe made therein without departing from the spirit or scope of theinvention as defined by the following claims.

What is claimed is:
 1. A display panel comprising: a substrate includinga front display area, a corner display area extending from a corner ofthe front display area, and a peripheral area outside the corner displayarea, wherein the corner display area includes a first corner displayarea and a second corner display area, the first corner display areaincludes extension portions extending in a direction away from the frontdisplay area, and cutout portions are defined in the first cornerdisplay area between the extension portions; a first corner drivingcircuit positioned in the second corner display area and electricallyconnected to each of a front pixel arranged in the front display areaand a corner pixel arranged in the first corner display area; a secondcorner driving circuit positioned in the second corner display area,electrically connected to the corner pixel arranged in the first cornerdisplay area, and not electrically connected to the front pixel; and aload portion positioned in the peripheral area and electricallyconnected to the second corner driving circuit.
 2. The display panel ofclaim 1, wherein the extension portions include a first extensionportion in which the load portion is not positioned and a secondextension portion in which the load portion is positioned, the cornerpixel electrically connected to the first corner driving circuit isarranged in the first extension portion along an extending direction ofthe first extension portion, and, the corner pixel electricallyconnected to the second corner driving circuit is arranged in the secondextension portion along an extending direction of the second extensionportion.
 3. The display panel of claim 2, further comprising: a voltageline positioned in the second corner display area; a corner voltage lineextending in the extending direction of the second extension portion inthe second extension portion, and including an end electricallyconnected to the voltage line and another end electrically connected tothe load portion; and a corner signal line extending in the extendingdirection of the second extension portion in the second extensionportion, and including an end electrically connected to the secondcorner driving circuit and another end electrically connected to theload portion.
 4. The display panel of claim 3, wherein the load portionincludes a first conductive layer and a second conductive layer, whereinthe second conductive layer is disposed on the first conductive layerand overlapping the first conductive layer, the another end of thecorner signal line is electrically connected to the first conductivelayer, and the another end of the corner voltage line is electricallyconnected to the second conductive layer.
 5. The display panel of claim4, wherein the corner pixel is electrically connected to a corner pixelcircuit including at least one thin-film transistor and at least onestorage capacitor, the at least one thin-film transistor includes asemiconductor layer, a gate electrode overlapping the semiconductorlayer, and a source electrode and a drain electrode which areelectrically connected to the semiconductor layer, the at least onestorage capacitor includes a lower electrode and an upper electrode,wherein the lower electrode is disposed in a same layer as the gateelectrode, and the upper electrode overlaps the lower electrode, thefirst conductive layer and at least one selected from the gate electrodeand the lower electrode have a same layer structure as each other andinclude a same material as each other, and the second conductive layerand the upper electrode have a same layer structure as each other andinclude a same material as each other.
 6. The display panel of claim 3,wherein the load portion includes a first conductive layer, a secondconductive layer disposed on the first conductive layer and overlappingthe first conductive layer, and a third conductive layer disposed on thesecond conductive layer and overlapping the second conductive layer, theanother end of the corner signal line is electrically connected to thefirst conductive layer, and the another end of the corner voltage lineis electrically connected to the third conductive layer.
 7. The displaypanel of claim 6, wherein the corner pixel is electrically connected toa corner pixel circuit including at least one thin-film transistor andat least one storage capacitor, the at least one thin-film transistorincludes a semiconductor layer, a gate electrode overlapping thesemiconductor layer, and a source electrode and a drain electrode whichare electrically connected to the semiconductor layer, the at least onestorage capacitor includes a lower electrode and an upper electrode,wherein the lower electrode is disposed in a same layer as the gateelectrode, and the upper electrode overlaps the lower electrode, thefirst conductive layer and the semiconductor layer have a same layerstructure as each other and include a same material as each other, thesecond conductive layer and at least one selected from the gateelectrode and the lower electrode have a same layer structure as eachother and include a same material as each other, and the thirdconductive layer and the upper electrode have a same layer structure aseach other and include a same material as each other.
 8. The displaypanel of claim 2, wherein, when viewed in a direction perpendicular toan upper surface of the substrate, a shape of an outer edge of the loadportion correspond to a shape of an outer edge of an extension portionin which the load portion is positioned, among the extension portions.9. The display panel of claim 2, wherein one load portion is positionedin each second extension portion.
 10. The display panel of claim 2,wherein two load portions are arranged in each second extension portion.11. The display panel of claim 1, wherein the corner pixel arranged inthe second corner display area overlaps the first corner driving circuitor the second corner driving circuit.
 12. The display panel of claim 1,wherein the display area further includes a side display area extendingfrom a side surface of the front display area, and a side pixel isarranged in the side display area.
 13. A display apparatus comprising: adisplay panel including a front display area, a corner display areaextending from a corner of the front display area and bent at a presetradius of curvature, and a peripheral area outside the corner displayarea, wherein the corner display area includes a first corner displayarea and a second corner display area; and a cover window covering thedisplay panel and having a shape corresponding to a shape of the displaypanel, wherein the display panel includes: a first corner drivingcircuit positioned in the second corner display area and electricallyconnected to each of a front pixel arranged in the front display areaand a corner pixel arranged in the first corner display area; a secondcorner driving circuit positioned in the second corner display area,electrically connected to the corner pixel arranged in the first cornerdisplay area, and not electrically connected to the front pixel; and aload portion positioned in the peripheral area and electricallyconnected to the second corner driving circuit.
 14. The displayapparatus of claim 13, wherein the first corner display area includesextension portions extending in a direction away from the front displayarea, the extension portions include a first extension portion in whichthe load portion is not positioned and a second extension portion inwhich the load portion is positioned, the corner pixel electricallyconnected to the first corner driving circuit is arranged in the firstextension portion along an extending direction of the first extensionportion, and, the corner pixel electrically connected to the secondcorner driving circuit is arranged in the second extension portion alongan extending direction of the second extension portion.
 15. The displayapparatus of claim 14, further comprising: a voltage line positioned inthe second corner display area; a corner voltage line extending in theextending direction of the second extension portion in the secondextension portion, and including an end electrically connected to thevoltage line and another end electrically connected to the load portion;and a corner signal line extending in the extending direction of thesecond extension portion in the second extension portion, and includingan end electrically connected to the second corner driving circuit andanother end electrically connected to the load portion.
 16. The displayapparatus of claim 15, wherein the load portion includes a firstconductive layer and a second conductive layer, wherein the secondconductive layer is disposed on the first conductive layer andoverlapping the first conductive layer, the another end of the cornersignal line is electrically connected to the first conductive layer, andthe another end of the corner voltage line is electrically connected tothe second conductive layer.
 17. The display apparatus of claim 16,wherein the corner pixel is electrically connected to a corner pixelcircuit including at least one thin-film transistor and at least onestorage capacitor, the at least one thin-film transistor includes asemiconductor layer, a gate electrode overlapping the semiconductorlayer, and a source electrode and a drain electrode which areelectrically connected to the semiconductor layer, the at least onestorage capacitor includes a lower electrode and an upper electrode,wherein the lower electrode is disposed in a same layer as the gateelectrode, and the upper electrode overlaps the lower electrode, thefirst conductive layer and at least one selected from the gate electrodeand the lower electrode have a same layer structure as each other andinclude a same material as each other, and the second conductive layerand the upper electrode have a same layer structure as each other andinclude a same material as each other.
 18. The display apparatus ofclaim 15, wherein the load portion includes a first conductive layer, asecond conductive layer disposed on the first conductive layer andoverlapping the first conductive layer, and a third conductive layerdisposed on the second conductive layer and overlapping the secondconductive layer, the another end of the corner signal line iselectrically connected to the first conductive layer, and the anotherend of the corner voltage line is electrically connected to the thirdconductive layer.
 19. The display apparatus of claim 18, wherein thecorner pixel is electrically connected to a corner pixel circuitincluding at least one thin-film transistor and at least one storagecapacitor, the at least one thin-film transistor includes asemiconductor layer, a gate electrode overlapping the semiconductorlayer, and a source electrode and a drain electrode which areelectrically connected to the semiconductor layer, the at least onestorage capacitor includes a lower electrode and an upper electrode,wherein the lower electrode is disposed in a same layer as the gateelectrode, and the upper electrode overlaps the lower electrode, thefirst conductive layer and the semiconductor layer have a same layerstructure as each other and include a same material as each other, thesecond conductive layer and at least one selected from the gateelectrode and the lower electrode have a same layer structure as eachother and include a same material as each other, and the thirdconductive layer and the upper electrode have a same layer structure aseach other and include a same material as each other.
 20. The displayapparatus of claim 14, wherein, on a plan view, a shape of an outer edgeof the load portion corresponds to a shape of an outer edge of anextension portion in which the load portion is positioned, among theextension portions.